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1 of 18 rev: 071305 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata. features ? integrated real-time clock (rtc), power- fail control circuit, and nv ram controller ? clock registers are accessed identically to the static ram; these registers are resident in the 16 top ram locations ? century register ? greater than 10 years of timekeeping and data retention in the absence of power with small lithium coin cell(s) and low-leakage sram ? precision power-on reset ? programmable w alarm ? bcd-coded year, month, date, day, hours, minutes, and seconds with automatic leap- year compensation valid up to the year 2100 ? battery voltage-level indicator flag ? power-fail write protection allows for ? 10% v cc power-supply tolerance ? underwriters laboratory (ul) recognized pin configuration ordering information part temp range voltage (v) pin-package top mark* ds1558 watchdog clock with nv ram control www .maxim-ic.com atchdog timer and rtc ds1558w -40c to +85c 3.3 48 tqfp (7 x 7 x 1mm) ds1558d ds1558w+ -40c to +85c 3.3 48 tqfp (7 x 7 x 1mm) ds1558d ds1558w-trl -40c to +85c 3.3 48 tqfp (7 x 7 x 1mm) ds1558d ds1558w+trl -40c to +85c 3.3 48 tqfp (7 x 7 x 1mm) ds1558d ds1558y -40c to +85c 5.0 48 tqfp (7 x 7 x 1mm) ds1558b ds1558y+ -40c to +85c 5.0 48 tqfp (7 x 7 x 1mm) ds1558b ds1558y-trl -40c to +85c 5.0 48 tqfp (7 x 7 x 1mm) ds1558b ds1558y+trl -40c to +85c 5.0 48 tqfp (7 x 7 x 1mm) ds1558b + denotes a lead(pb)-free/rohs-compliant device. * a ?+? anywhere on the top mark indicates a lead-free device. a18 a16 a12 a6 a4 a3 a2 a1 a5 a7 a14 n.c. v cco v cc n.c. a 17 gnd r st n.c. n.c. dq0 dq1 dq2 dq6 v bat1 w e i rq / ft a 8 o e a 10 c e x 1 gnd v bat 2 a 15 a 13 o er a 9 a 11 35 36 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 10 12 11 9 48 47 46 45 44 43 42 41 40 39 38 37 cer dq7 dq5 dq4 dq3 gnd a0 ds1558 x 2 n.c. tqfp top view
ds1558 2 of 18 pin description pin name function 1, 13, 39 n.c. no connection 41, 4 3 2 a18 3 a16 4 a14 5 a12 6 a7 7 a6 8 a5 9 a4 10 a3 11 a2 12 a1 14 a0 27 a10 29 a11 30 a9 31 a8 32 a13 36 a15 44 a17 r ad ess decode. t e inputs to determine read o write cycle should cted to the attached sram or to the address inputs fo whether or not a rtc registers. dr h ds1558 us es the address r be dire 15 dq0 16 dq1 17 dq2 19 dq3 20 dq4 21 dq5 22 dq6 23 dq7 data input/outputs. data input/output pins for the rtc registers. 18, 45, 48 gnd ground 24 cer active-low chip-enable ram. ce is passed through to cer , with an added propagation delay. when the signals on a0?a18 match an rtc address, cer is held high, disabling the sram. if oe is also low, the rtc outputs data on dq0?dq7. 25 oer active-low output-enable ram. oe is passed through to oer , with an added propagation delay. when the signals on a0?a18 match an rtc address, cer is held high, disabling the sram. if ce is also low, the rtc outputs data on dq0?dq7. 26 ce active-low chip-enable input. used to access the rtc and the external sram. 28 oe active-low output-enable input. used to access the rtc and the external sram. 33 irq/ ft active-low interrupt/frequency-test output. this pin is used to output the alarm interrupt or the frequency test signal. it is open drain and requires an external pullup resistor. 34 we active-low write enable. used to write data to the rtc registers.
ds1558 3 of 18 pin crip tin name on des tion (con ued) pin functi 35 v bat1 37 v bat2 puts fo y sta el energy source. battery ust be betw r p ation. ul recognized to ainst re e cha ed ium battery. if only one used, it should b nd uld be grounded. see ns of acceptabil c.com/techsupport/qa/ntrl.htm battery is battery in r an ndard +3v lith ium c l or other voltage m held een 2.5v and 3.7v fo roper oper ensure ag vers rging current when us with a lith e attached to v bat1 , a v bat2 sho ?conditio ity? at www.maxim-i . 38 rst cc is out of tolerance. on power-up, the system to stabilize. the active-low power-on reset output (open drain). this pin is an output used to signal rst is held low for a period of time to allow rtc and sram are not accessible while rst is active. this pin is open drain and requires an external pullup resistor. that v 40 v cco v cc output to ram. while v cc is above v bat , the external sram is powered by v cc . when v cc is below the battery level, the sram is powered by one of the v bat inputs. 42 v cc power-supply input. dc power is provided to the device on these pins. v cc is the +5v input. when 5v (or 3.3v for the 3.3v version) is applied within normal limits, the device is fully accessible and data can be written a nd read. reads and writes are inhibited when a 3v battery is connected to the device and v cc is v tp . however, the timekeeping function continues unaffected by the lower input voltage. as v cc falls below v bat , the ram and rtc are switched over to the external power supply (nominal 3.0v dc) at v bat . 46 x1 47 x2 connections for standard 32.768khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 6pf. for more information about crystal selection a nd crystal layout considerations, refer to application note 58: crystal considerations with dallas real-time clocks . the ds1558 can also be driven by an external 32.768khz oscillator. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is floated. typical operating circuit
ds1558 4 of 18 d cr on s1 s n, year 2000-compliant (y2kc), real-tim e clock/calendar with an rtc alarm, watchdog timer, power-on reset, battery monitor, and nv sram controller. user access to all registers within the ds1558 is accomplished with a byte-wide interface as shown in figure 1. the rtc registers contain century, year, month, date, day, hours, minutes, a nd seconds data in 24-hour bcd fo at. corrections for day of month and leap year are made automatically. the ds1558 maps the rtc register s into the sram address space and constantly monitors a0?a18. w n any the es ipti the d 558 i a full-functio rm he of upper 16 address loca tions are accessed, the ds1558 inhibits cer and oer to the s m, an dir ds1558 can be used w sra up addresses. smaller srams can be used, provided that the unused upper address lines on the ds1558 are connected to v cc . the rtc registers are double-buffered into an internal and external set. the user has direct access to the external set. clock/calendar updates to the external set of registers ca n be disabled and enabled to allow th ser to ess static data. assuming the internal oscillator is turned on, the internal set of registers is continuously updated; this occurs regardless of extern al register settings to guarantee that accurate rtc in ation is always maintained. the ds1558 has interrupt ( ra d re ects reads and writes to the rtc registers within the ds1558. the to 524,272 ith ms e u a cc form irq /ft) and reset ( rst ) outputs that can be used to control cpu activity. the irq / ter terrupt when the rtc register values m h use grammed alarm values. the interrupt is always available while th e device is powered from th ystem ply, and it can be programmed to occur when in the battery-backed state to serve as a wake-up. the ft in rupt output can be used to generate an external in atc r-pro e s sup system irq /ft output can also be used as a cpu watchdog timer. cpu activity is monitored and an interrupt or rese t output are activated if the correct activity is not detected within programm i ower-down or failure and hold the cpu ; the ed lim ts. the ds1558 power-on reset can be us ed to detect a system p in a safe reset state until normal power returns and stabilizes rst output is used for this function. t ds155 also tects the data in the clock and sram against out-of-tolerance v conditions by inhibiting the he 8 contains its own po wer-fail circuitry, which automatically pro cci ce input when the v cc supply enters an out-of-tolerance condition. w t , the external battery is s hed u ovides a high degree of data security during unpredictable cc levels. hen v cci goes below the level of v ba pply energy to th e clock and the external sram. th is feature pr witc on to s system operation brought on by low v
ds1558 5 of 18 figure 1. block diagram es v cc table 1. operating mod ce oe we dq0?dq7 mode power v ih x x high-z deselect standby v il x v il d in write active v il v il v ih d out read active v cc > v pf v il v ih v ih high-z read active v so < v cc < v pf x x x high-z deselect cmos standby v cc < v so < v pf x x x high-z data retention battery current data read mode the ds1558 is in the read mode whenever ce is low and we is high. the device architecture allows gh access to any valid address location. va lid data is available at the dq pins within t aa after the last address input is stable, provided that ripple-th rou ce and oe access times are satisfied. if ce or oe access et, valid data is available at the latter of chip-enable access (t cea ) or at output-enable (t oea ). the state of the data input/out put pins (dq) is controlled by tim es are not m access tim e ce and oe . if the ated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while outputs are activ ce and oe remain valid, output data remains valid for output-data hold time ), but then goes indeterminate until the next a ddress acces s. (t oh note: any u s the rtc. nused upper address pins must be connected to v cc to properly addres
ds1558 6 of 18 data write mode the ds1558 is in the write mode whenever we and ce are in their active state. the referenced to the latter occurring transition of start of a write is we or ce . the addresses must be hel the cycle. d valid throughout ce and we must return inactive for a minimum of t prior to the initiation of a subsequent read or write cycle. data in must be valid t prior to the wr ds end of the write and remain valid for t dh afterward. in a typical application, the oe signal is high during a write cycle. however, oe can be active ten if provided that care is ta ken with the data bus to avoid bus con tion. oe is lo w prior to we ress inputs. a low transitioning low, the data bus can become active w ith read data defined by the add transition on we then disables the outputs t wez after we goes active. data retention mode the 5v device is fully accessible and data can be written and read only when v cc i however, when v cc is below the power-fail point v pf (point at which write prot internal clock registers and sram are blocked from any access. when v falls below the batter s greater than v pf . ection occurs), the cc y switch point v so (battery supply level), device power is switched from the v cc pin to the backup battery. rtc inal levels. s greater than v pf . he device power is c t . if v pf is greater cc drops v cc is returned to all control, data, and address signa ls must be powered down when v cc is powered down. 558 internal clock current is less than g. no external protection com ponents are required, and none should be used. the ds1558 has two battery pins that operate independently; the ds1558 selects the higher of the two inputs. if only one battery is used, the batter y should be attached to v bat1 , and v bat2 should be grounded. internal battery monitor the ds1558 constantly monitors the ba ttery voltage of the internal battery. the battery-low flag (blf) bit of the flags register (b4 of 7fff 0h) is not writable and should always be a 0 when read. if a 1 is ever present, both battery inputs are below 1.8v and both the contents of the rtc and ram are questionable. power-on reset a temperature-compensated comparator circuit monitors the level of v cc . when v cc falls to the power- fail trip point, the operation and sram data are m aintained from the battery until v cc is returned to nom the 3.3v device is fully accessible and data can be written and read only when v cc i when v cc falls below v pf , access to the device is inhibited. if v pf is less than v so , t switched from v c o the internal backup lithium battery w hen v cc drops below v pf than v so , the device power is switched from v cc to the internal backup lithium battery when v below v so . rtc operation and sram data are ma intained from the battery until nom inal levels. battery longivity the battery lifetime is dependent on the ram ba ttery standby current and the ds1 oscillator current. the to tal battery current is i osc + i cco . when v cc is above v pf , i bat 50na. the ds1558 has an internal circ uit to prevent battery chargin rst signal (open drain) is pulled low. when v cc returns to nominal levels, the rst signal continues to be pulled low for a period of 40ms to 200ms. the pow er-on reset function is independent of the rtc oscillator and thus is operational whether or not the oscillator is enabled.
ds1558 7 of 18 clock operations table 2 and the following paragraphs describe the operation of the rtc, alarm, and watchdog functions. table 2. ds1558 register map data addr ge ess b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function/ran 7ffff 00?99 h 10 year year year 7fff 01?12 eh x x x 10 m month month 7fffd 01?31 h x x 10 date date date 7fff 01?07 ch x ft x x x day day 7fff 00?23 bh x x 10 hour hour hour 7fffah x 10 minutes minutes minutes 00?59 7fff9 h osc 10 seconds second s seconds 00?59 7fff 00?39 8h w r 10 century century control 7fff7h ? wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 7fff6h ae y ab e y y y y y interrupts ? 7fff5h am4 y 10 date date alarm date 01?31 7ff a 1 hours alarm hours 00?23 f4h m3 y 0 hours 7fff3h a 1 inut minutes alarm minutes 00?59 m2 0 m es 7fff2h a 1 co se conds alarm seconds 00?59 m1 0 se nds 7fff1h y y y unused ? y y y y y 7fff0h w 0 f 0 flags ? f af bl 0 0 0 x = unused, rea d/writeable under write and y = unused, read/wri teable without write and read bit control blf = batter w flag clock oscillator control the oscillator can be turned off to mini mi the battery. the r ead bit control ae = alarm flag enable ft = frequency test bit osc = oscillator start/stop bit abe = alarm in backup-battery mode enable w = write bit am1?am4 = alarm mask bits r = read bit wf = watchdog flag wen = watchdog enable bit af = alarm flag bmb0?bmb4 = watchdog multiplier bits 0 = reads as a 0 and cannot be changed rb0?rb1 = watchdog resolution bits y lo ze current drain from osc the seconds register (b 7 of 7fff9h). setting bit is the msb of osc to a 1 stops the oscillator; setting to a 0 starts the oscillator. the initial state of osc is not guaranteed. when power is applied for the first tim e, the osc bit should be enabled. quency can be verified by se bit and monitoring the oscillator operation and fre tting the f t irq /ft pin for 512hz. oscillator startup time oscillator startup times are hi ghly dependent upon crystal character istics and layout. high esr and excessive capacitive loads are the majo r contributors to long startup time s. a circuit using a crystal with the recommended characteristics and following the recommended layout usually starts within 1 second.
ds1558 8 of 18 of double-buffered ad without register tinue while in this he control register t halt is issued, alt com t u me within 1 second after the read bit is set to s. the read bit m inimum of 500 s to ensure the extern e the read bit, halts updates to the 7fff8h?7ffffh registers. after setting the write bit to a 1, rtc regi sters can be loaded rite bit to a 0 then resume. y of the clock is dependent upon the accur acy of the crystal and the accuracy of the match load for which the crystal was by temperature shifts. external o the oscillator circuit can result in the clock running fast. refer to application n. reading the clock when reading the rtc data, it is recomme ed to halt updates to the external set rtc registers. this puts the external registers into a static state, allowi ng data to be re values changing during the re ad process. normal updates to the internal registers con state. external updates are halted when a 1 is writte n into the read bit, b6 of t (7fff8h). as long as a 1 remains in the control register read bit, updating is halted. af the registers reflect the rt c count (day, date, and time) that was cu rrent at the moment is issued. normal updates to the extern al se f registers nd o u er a the h mand al re st be a 0 for a m s a 0 for a minimum of 500 ? ? registers are updated. setting the clock the msb bit, b7, of the control register is the write bit. setting the write bit to a 1, lik with the desired rtc count (day, date, and time) in 24-hour bcd format. setting th e w transfers the values written to the internal rt c registers and allows normal operation to clock accuracy the accurac between the capacitive load of the oscillator circui t and the capacitive trimmed. additional error is added by the crystal-fre quency drift caused circuit noise coupled int note 58 ?crystal considerations with dallas re al-time clocks? for detailed informatio frequency test mode the ds1558 frequency test mode uses the open-drain irq /ft output. with the osc illator running, the irq /ft output toggles at 512hz when th e ft bit is a 1, the alarm-flag enable bit (ae) is a 0, and the r the watchdog register is reset (register 7fff7h = 00h). the watchdog-enable bit (wds) is a 1, o irq /ft of the 32.768khz output and the frequency test mode can be used as a measure of the actual frequency rtc oscillator. the irq /ft pin is an open-drain output that requires a pullup resistor for proper operation. the ft bit is cleared to a 0 on power-up. . register 7fff6 h the ae and abe bits must be set as described below for the using the clock alarm the alarm settings and control for the ds1558 resi de within registers 7fff2h?7fff5h contains two alarm-enable bits: alarm enable (ae) and alarm in backup enable (abe). irq /ft output to be activated for a matched alarm condition. the alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. it can also be programmed to go o ff while the ds1558 is in th e battery-backed state of operation to serve as a system wa ke-up. alarm mask bits am1?am4 control the alarm mode. table 3 ions not listed in the table defa ult to the once-per-second mode to notify the user of an incorrect alarm setting. shows the possible settings. configurat
ds1558 9 of 18 am1 alarm rate table 3. alarm mask bits am4 am3 am2 1 1 1 1 once per second 1 1 1 0 w he ec s ma n s ond tch 1 1 0 0 minutes and s match when second 1 0 0 hours, minutes, and seconds match 0 when 0 0 0 when date, hours, m s, and s s match 0 inute econd w he r c regis atch al arm s, af a 1. if ae is also set to a 1, the a ond ac i hen t t ter values m register setting is set to larm c ition t vates the irq /ft pin. the irq /ft signal by a or write to the flags register (address 7fff0h). w is cleared re ad hen ce h is ac tive, t e irq /ft si clear by having the address gnal can be ed stable for as short as 15ns and either oe or we active, ut is teed e cleared unless t rc is fulfilled (f ess ha s been s b not guaran to b igure 2). once the add r elected for at least 15ns, the irq al can be cleared i ate ut is eed to be c til t rc is re he alarm flag is also c by ad or e flags reg the flag e s until the end of the read/write cycle and the /ft sign mm edi ly, b not guarant leared un fulfilled (figu 3). t lea red a re write to th ister, but does not chang state irq /ft igna as b cl ed s l h een ear . the irq /ft pin can also be activated in ked mode. the the battery-bac irq /ft goes low if an alarm abe and ae are set. th he power-up transition, ted during power- up se can be read after system power-up ine if an alarm was generated d sequence. figure 4 illustrates alarm timing ttery mode and power-up states. occurs and both e abe and ae bits are cleared duri ng t but an alarm genera ts af. therefore, the af bit to determ uring the power-up during the backup-ba figure 2. clearing irq waveforms active figure 3. clearing irq waveforms
ds1558 10 of 18 figure 4. backup mode alarm waveforms he user program s the watchdog ount of timeout into the 8- bit watchdog register (address 7fff7h). the sto = 1 second, and ation of the 5-bit watchdog register ecified period, the or the watchdog register (7fff7h) is read or written. a 0, the w og using the watchdog timer the watchdog timer can be used to detect an out-of-control processor. t timer by setting the desired am five watchdog register bits bmb4?bmb0 re a bi nary multiplier and the two lower-order bits rb1?rb0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 11 = 4 seconds. the watchdog timeout value is then determined by the multiplic multiplier value with the 2-bit resolution value. (f or example: writing 00001110 in the = 3 x 1 second or 3 seconds.) if th e processor does not reset the timer within the sp watchdog flag (wf) is set and a processor interrupt is generated and stays active un til either wf is read the msb of the watchdog register is the watchdog st eering bit (wds). when set to activates the atchd irq /ft output when the watchdog times out. wds s hould not be written be initialized to a 0 if th e watchdog function is enabled. hdog register. the 0h to the watchdog atchdog register is power-on default states upon application of power to the device, th e following register bits are set to a 0: wds = 0, bmb0?bmb4 = 0, rb0?rb1 = 0, ae = 0, and abe = 0 all other bits are undefined. to a 1, and should the watchdog tim er resets when the processor perfor ms a read or write of the watc timeout period then starts over. the watchdog timer is disabled by writing a va lue of 0 register. the watchdog function is automatically disabled upon power-up and the w cleared.
ds1558 11 of 18 absolute m u tings voltage range on any pin relative to ground?????????????????..-0.3v to +6.0v storage temperature range????????????????????????.-55 ?c to +125 ?c soldering t perature????????????????.see ipc/jedec j-std-020 specification this is a stress rating only a function pera those indicated in the operation sections of this tion ot implied. expo ded periods of time can affect a t its notes axi m m ra em nd al o t ion of the device at these or any other condition s beyond sure to absolute maximum ra ting conditions for exten specifica is n reliability. recommended dc oper ating conditions (v cc = 3.3v 10% or 5v 10%, t = -40c to +85c.) parameter symbol min yp max un v cc = +5v ? 10% 2.2 v cc + 0.3v logic 1 voltage (all inputs) c = +3.3v ? 10% v ih v c 2.0 v cc v 1 + 0.3v v cc = +5v ? 10% -0.3 +0.8 l ic 0 voltage (all inputs) v cc = +3.3v ? 10% v il -0.3 +0.6 og v 1 battery voltage v bat 2.5 3.3 3.7 v
ds1558 12 of 18 dc electrical characteristics (v cc = +3.3v 10% or +5v 10%, t = -40c to +85c.) notes a parameter symbol min typ max units active suppl ma 2, 3 y current, +5v i cc 6 25 active suppl ma 2, 3 y current, +3.3v i cc 4 15 ttl standby, +5v ( ce = v ih ) i cc1 3 6 ma 2, 3 ttl standby, +3.3v ( ce = v ih ) i cc1 2 6 ma 2, 3 cmos standb ( y current, +5v ce ?? v cc ma 2, 3 - 0.2v) i cc2 2 6 cmos standb y current, +3.3v ( ce ?? v - 0.2v) cc i cc2 1 2 ma 2, 3 input leakage current (any input) i il -1 +1 ? a output leakage current (any output) i ol -1 +1 ? a output logic 1 voltage (i out = -1.0ma) v oh 2.4 v 1 i out = 2.1ma, dq0?dq7 outputs v ol1 0.4 v 1 output logic 0 voltage i out = 7.0ma, irq /ft and rst outputs v ol2 0.4 v 1, 5 write protection voltage, +5v v pf 4.20 4.37 4.50 v 1 write protection voltage, +3.3v v 2.75 2.88 2.97 pf v 1 battery switchover voltage, +5v v so v bat v 1 battery switchover voltage, +3.3v v so v pf v 1, 4 battery curre 0.3 0.5 a 6,7 nt osc on i osc battery current osc o ff i backup 100 na 7 output voltage i cco = 70ma, +5v v cc01 v cc1 - 0.3 v ? output voltage i cco = 40ma, +3.3v v cc01 v cc1 - 0.3 v ? output voltage i cco = 10 a v cc02 v bat - 0.2 v bat - 0.031 v ? 10 crystal specifications * parameter symbol min typ max units notes nominal frequency f o 32.768 khz series resistance esr 45 k ? load capacitance c l 6 pf *the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations for dallas real-time clocks for additional s pecifications.
ds1558 13 of 18 cc cc read cycle, ac characteristics (v = +3.3v 10% or +5v 10%, t = -40c to +85c.) (figure 5) cc a v = +5.5v 10% v = +3.3v 10% parameter symbol min max min max units notes read cycle time t rc 70 120 ns address access time t aa 70 120 ns ce to dq low-z t cel 5 5 ns ce acce cea 7 ns ss time t 0 120 ce data off 40 ns time t cez 25 oe to dq low-z t oel 5 5 ns oe access ti me t oea 35 100 ns oe data of f time ez 25 35 ns t o output hold from address t oh 5 5 ns ce to cer propagation delay, +5v t cepd 15 ns oe to oer propagation delay, +5v t oepd 20 ns ce to cer propagation delay, +3.3v t cepd 30 ns oe to oer propagation delay, +3.3v t oepd 40 ns figure 5. read cycle timing diagram
ds1558 14 of 18 s (v cc = + +5v 10% 0 +8 ) r d 7) v cc = +5.0v 10% = +3.3v 1 write cycle, ac characteristic 3.3v 10% or , t a = -4 c to 5c. (figu e 6 an figure v cc 0% parameter symbo min m x max units notes l a min write cycle tim e t wc 70 120 ns address access t e im t as 0 0 ns we pulse width t wew 50 100 ns ce pulse width t cew 60 110 ns data setup time t ds 30 80 ns data hold time t dh1 5 5 ns 8 data hold time t dh2 5 5 ns 9 address hold time t ah1 5 0 ns 8 address hold time t ah2 5 5 ns 9 we data off ti t wez 25 40 ns me write recov ery tim t wr 5 10 ns e
ds1558 15 of 18 ble controlled figure 6. write cycle timing, write-ena figure 7. write cycle timing, chip-enable controlled
ds1558 16 of 18 (v c , t a t aramete symbol in typ max units notes power-up/down ch aracteristics c = +5v ? 10% = -40c o +85c.) (figure 8) p r m ce or we at v ih , before power-down t 0 ? s pd v e: v pf(max) to min) ? s cc fall tim v pf( t f 300 v cc fall time: v pf(min) to v so 10 ? s t fb v cc rise time: v pf(min) to max) t 0 ? s v pf( r v pf to rst high t rec 40 200 ms figure 8. +5v power-up/down waveform timing
ds1558 17 of 18 power-up/down ch aracteristics (v cc ? es = +3.3v 10%, t a = -40c to +85c.) (figure 9) parameter symbol min typ max units not ce or we at v ih , before power-down t pd 0 ? s v cc fall time: v pf(max) to v pf(min) t f 300 ? s v cc rise time: v pf(min) to v pf(max) t r 0 ? s v pf to rst high t rec 40 200 ms figure 9. +3.3v power-up/down waveform timing capacitance (t a = +25 ?c) parameter symbol min typ max units note s capacitance on all input pins c in 7 pf 1 capacitance on irq /ft, rst , and dq pins c io 10 pf 1
ds1558 18 of 18 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. output l input pulse levels: 0 to +3v ment reference le : es: 5ns notes: 2) typical valu es are at +25 ? c and nominal supplies. 3) outputs are open. ac test conditions oad: 25pf tim ing measure vels input: +1.5v output: +1.5v input pulse rise and fall tim 1) voltage referenced to ground. 4) battery switchover occurs at the lower of either the battery voltage or v pf . 5) the irq /ft and rst outputs are open drain. 6) using the recommended crystal on x1 and x2. 7) v cco , cer , and oer pins open. 8) t ah1 , t dh1 are measured from we going high. 9) t ah2 , t dh2 are measured from ce going high. 10) typical measured with v bat at 3.0v. typical with i cco = 100 a and v bat = 3.0v is v bat - 0.322. package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 48 tqfp c48+1 21-0054

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